/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_ROM_REGISTERS_H__
#define __HW_ROM_REGISTERS_H__

#include "MKL02Z4.h"
#include "fsl_bitband.h"

/*
 * MKL02Z4 ROM
 *
 * System ROM
 *
 * Registers defined in this header file:
 * - HW_ROM_ENTRYn - Entry
 * - HW_ROM_TABLEMARK - End of Table Marker Register
 * - HW_ROM_SYSACCESS - System Access Register
 * - HW_ROM_PERIPHID4 - Peripheral ID Register
 * - HW_ROM_PERIPHID5 - Peripheral ID Register
 * - HW_ROM_PERIPHID6 - Peripheral ID Register
 * - HW_ROM_PERIPHID7 - Peripheral ID Register
 * - HW_ROM_PERIPHID0 - Peripheral ID Register
 * - HW_ROM_PERIPHID1 - Peripheral ID Register
 * - HW_ROM_PERIPHID2 - Peripheral ID Register
 * - HW_ROM_PERIPHID3 - Peripheral ID Register
 * - HW_ROM_COMPIDn - Component ID Register
 *
 * - hw_rom_t - Struct containing all module registers.
 */

#define HW_ROM_INSTANCE_COUNT (1U) /*!< Number of instances of the ROM module. */

/*******************************************************************************
 * HW_ROM_ENTRYn - Entry
 ******************************************************************************/

/*!
 * @brief HW_ROM_ENTRYn - Entry (RO)
 *
 * Reset value: 0x00000000U
 *
 * The System ROM Table begins with "n" relative 32-bit addresses, one for each
 * debug component present in the device and terminating with an all-zero value
 * signaling the end of the table at the "n+1"-th value. See Chip Configuration
 * chapter for the debug components these registers point to. It is hardwired to
 * specific values used during the auto-discovery process by an external debug
 * agent.
 */
typedef union _hw_rom_entryn
{
    uint32_t U;
    struct _hw_rom_entryn_bitfields
    {
        uint32_t ENTRY : 32;           /*!< [31:0] ENTRY */
    } B;
} hw_rom_entryn_t;

/*!
 * @name Constants and macros for entire ROM_ENTRYn register
 */
/*@{*/
#define HW_ROM_ENTRYn_COUNT (3U)

#define HW_ROM_ENTRYn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))

#define HW_ROM_ENTRYn(x, n)      (*(__I hw_rom_entryn_t *) HW_ROM_ENTRYn_ADDR(x, n))
#define HW_ROM_ENTRYn_RD(x, n)   (HW_ROM_ENTRYn(x, n).U)
/*@}*/

/*
 * Constants & macros for individual ROM_ENTRYn bitfields
 */

/*!
 * @name Register ROM_ENTRYn, field ENTRY[31:0] (RO)
 *
 * Entry 0 (MTB) is hardwired to 0xFFFF_E003; Entry 1 (MTBDWT) to 0xFFFF_F003;
 * Entry 2 (CM0+ ROM Table) to 0xF00F_D003.
 */
/*@{*/
#define BP_ROM_ENTRYn_ENTRY  (0U)          /*!< Bit position for ROM_ENTRYn_ENTRY. */
#define BM_ROM_ENTRYn_ENTRY  (0xFFFFFFFFU) /*!< Bit mask for ROM_ENTRYn_ENTRY. */
#define BS_ROM_ENTRYn_ENTRY  (32U)         /*!< Bit field size in bits for ROM_ENTRYn_ENTRY. */

/*! @brief Read current value of the ROM_ENTRYn_ENTRY field. */
#define BR_ROM_ENTRYn_ENTRY(x, n) (HW_ROM_ENTRYn(x, n).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_TABLEMARK - End of Table Marker Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_TABLEMARK - End of Table Marker Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * This register indicates end of table marker. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_tablemark
{
    uint32_t U;
    struct _hw_rom_tablemark_bitfields
    {
        uint32_t MARK : 32;            /*!< [31:0]  */
    } B;
} hw_rom_tablemark_t;

/*!
 * @name Constants and macros for entire ROM_TABLEMARK register
 */
/*@{*/
#define HW_ROM_TABLEMARK_ADDR(x) ((x) + 0xCU)

#define HW_ROM_TABLEMARK(x)      (*(__I hw_rom_tablemark_t *) HW_ROM_TABLEMARK_ADDR(x))
#define HW_ROM_TABLEMARK_RD(x)   (HW_ROM_TABLEMARK(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_TABLEMARK bitfields
 */

/*!
 * @name Register ROM_TABLEMARK, field MARK[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
/*@{*/
#define BP_ROM_TABLEMARK_MARK (0U)         /*!< Bit position for ROM_TABLEMARK_MARK. */
#define BM_ROM_TABLEMARK_MARK (0xFFFFFFFFU) /*!< Bit mask for ROM_TABLEMARK_MARK. */
#define BS_ROM_TABLEMARK_MARK (32U)        /*!< Bit field size in bits for ROM_TABLEMARK_MARK. */

/*! @brief Read current value of the ROM_TABLEMARK_MARK field. */
#define BR_ROM_TABLEMARK_MARK(x) (HW_ROM_TABLEMARK(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_SYSACCESS - System Access Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_SYSACCESS - System Access Register (RO)
 *
 * Reset value: 0x00000001U
 *
 * This register indicates system access. It is hardwired to specific values
 * used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_sysaccess
{
    uint32_t U;
    struct _hw_rom_sysaccess_bitfields
    {
        uint32_t SYSACCESS : 32;       /*!< [31:0]  */
    } B;
} hw_rom_sysaccess_t;

/*!
 * @name Constants and macros for entire ROM_SYSACCESS register
 */
/*@{*/
#define HW_ROM_SYSACCESS_ADDR(x) ((x) + 0xFCCU)

#define HW_ROM_SYSACCESS(x)      (*(__I hw_rom_sysaccess_t *) HW_ROM_SYSACCESS_ADDR(x))
#define HW_ROM_SYSACCESS_RD(x)   (HW_ROM_SYSACCESS(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_SYSACCESS bitfields
 */

/*!
 * @name Register ROM_SYSACCESS, field SYSACCESS[31:0] (RO)
 *
 * Hardwired to 0x0000_0001
 */
/*@{*/
#define BP_ROM_SYSACCESS_SYSACCESS (0U)    /*!< Bit position for ROM_SYSACCESS_SYSACCESS. */
#define BM_ROM_SYSACCESS_SYSACCESS (0xFFFFFFFFU) /*!< Bit mask for ROM_SYSACCESS_SYSACCESS. */
#define BS_ROM_SYSACCESS_SYSACCESS (32U)   /*!< Bit field size in bits for ROM_SYSACCESS_SYSACCESS. */

/*! @brief Read current value of the ROM_SYSACCESS_SYSACCESS field. */
#define BR_ROM_SYSACCESS_SYSACCESS(x) (HW_ROM_SYSACCESS(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID4 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID4 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid4
{
    uint32_t U;
    struct _hw_rom_periphid4_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid4_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID4 register
 */
/*@{*/
#define HW_ROM_PERIPHID4_ADDR(x) ((x) + 0xFD0U)

#define HW_ROM_PERIPHID4(x)      (*(__I hw_rom_periphid4_t *) HW_ROM_PERIPHID4_ADDR(x))
#define HW_ROM_PERIPHID4_RD(x)   (HW_ROM_PERIPHID4(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID4 bitfields
 */

/*!
 * @name Register ROM_PERIPHID4, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID4_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID4_PERIPHID. */
#define BM_ROM_PERIPHID4_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID4_PERIPHID. */
#define BS_ROM_PERIPHID4_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID4_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID4_PERIPHID field. */
#define BR_ROM_PERIPHID4_PERIPHID(x) (HW_ROM_PERIPHID4(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID5 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID5 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid5
{
    uint32_t U;
    struct _hw_rom_periphid5_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid5_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID5 register
 */
/*@{*/
#define HW_ROM_PERIPHID5_ADDR(x) ((x) + 0xFD4U)

#define HW_ROM_PERIPHID5(x)      (*(__I hw_rom_periphid5_t *) HW_ROM_PERIPHID5_ADDR(x))
#define HW_ROM_PERIPHID5_RD(x)   (HW_ROM_PERIPHID5(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID5 bitfields
 */

/*!
 * @name Register ROM_PERIPHID5, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID5_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID5_PERIPHID. */
#define BM_ROM_PERIPHID5_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID5_PERIPHID. */
#define BS_ROM_PERIPHID5_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID5_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID5_PERIPHID field. */
#define BR_ROM_PERIPHID5_PERIPHID(x) (HW_ROM_PERIPHID5(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID6 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID6 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid6
{
    uint32_t U;
    struct _hw_rom_periphid6_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid6_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID6 register
 */
/*@{*/
#define HW_ROM_PERIPHID6_ADDR(x) ((x) + 0xFD8U)

#define HW_ROM_PERIPHID6(x)      (*(__I hw_rom_periphid6_t *) HW_ROM_PERIPHID6_ADDR(x))
#define HW_ROM_PERIPHID6_RD(x)   (HW_ROM_PERIPHID6(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID6 bitfields
 */

/*!
 * @name Register ROM_PERIPHID6, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID6_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID6_PERIPHID. */
#define BM_ROM_PERIPHID6_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID6_PERIPHID. */
#define BS_ROM_PERIPHID6_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID6_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID6_PERIPHID field. */
#define BR_ROM_PERIPHID6_PERIPHID(x) (HW_ROM_PERIPHID6(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID7 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID7 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid7
{
    uint32_t U;
    struct _hw_rom_periphid7_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid7_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID7 register
 */
/*@{*/
#define HW_ROM_PERIPHID7_ADDR(x) ((x) + 0xFDCU)

#define HW_ROM_PERIPHID7(x)      (*(__I hw_rom_periphid7_t *) HW_ROM_PERIPHID7_ADDR(x))
#define HW_ROM_PERIPHID7_RD(x)   (HW_ROM_PERIPHID7(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID7 bitfields
 */

/*!
 * @name Register ROM_PERIPHID7, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID7_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID7_PERIPHID. */
#define BM_ROM_PERIPHID7_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID7_PERIPHID. */
#define BS_ROM_PERIPHID7_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID7_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID7_PERIPHID field. */
#define BR_ROM_PERIPHID7_PERIPHID(x) (HW_ROM_PERIPHID7(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID0 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID0 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid0
{
    uint32_t U;
    struct _hw_rom_periphid0_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid0_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID0 register
 */
/*@{*/
#define HW_ROM_PERIPHID0_ADDR(x) ((x) + 0xFE0U)

#define HW_ROM_PERIPHID0(x)      (*(__I hw_rom_periphid0_t *) HW_ROM_PERIPHID0_ADDR(x))
#define HW_ROM_PERIPHID0_RD(x)   (HW_ROM_PERIPHID0(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID0 bitfields
 */

/*!
 * @name Register ROM_PERIPHID0, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID0_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID0_PERIPHID. */
#define BM_ROM_PERIPHID0_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID0_PERIPHID. */
#define BS_ROM_PERIPHID0_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID0_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID0_PERIPHID field. */
#define BR_ROM_PERIPHID0_PERIPHID(x) (HW_ROM_PERIPHID0(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID1 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID1 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid1
{
    uint32_t U;
    struct _hw_rom_periphid1_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid1_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID1 register
 */
/*@{*/
#define HW_ROM_PERIPHID1_ADDR(x) ((x) + 0xFE4U)

#define HW_ROM_PERIPHID1(x)      (*(__I hw_rom_periphid1_t *) HW_ROM_PERIPHID1_ADDR(x))
#define HW_ROM_PERIPHID1_RD(x)   (HW_ROM_PERIPHID1(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID1 bitfields
 */

/*!
 * @name Register ROM_PERIPHID1, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID1_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID1_PERIPHID. */
#define BM_ROM_PERIPHID1_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID1_PERIPHID. */
#define BS_ROM_PERIPHID1_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID1_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID1_PERIPHID field. */
#define BR_ROM_PERIPHID1_PERIPHID(x) (HW_ROM_PERIPHID1(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID2 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID2 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid2
{
    uint32_t U;
    struct _hw_rom_periphid2_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid2_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID2 register
 */
/*@{*/
#define HW_ROM_PERIPHID2_ADDR(x) ((x) + 0xFE8U)

#define HW_ROM_PERIPHID2(x)      (*(__I hw_rom_periphid2_t *) HW_ROM_PERIPHID2_ADDR(x))
#define HW_ROM_PERIPHID2_RD(x)   (HW_ROM_PERIPHID2(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID2 bitfields
 */

/*!
 * @name Register ROM_PERIPHID2, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID2_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID2_PERIPHID. */
#define BM_ROM_PERIPHID2_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID2_PERIPHID. */
#define BS_ROM_PERIPHID2_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID2_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID2_PERIPHID field. */
#define BR_ROM_PERIPHID2_PERIPHID(x) (HW_ROM_PERIPHID2(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_PERIPHID3 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_PERIPHID3 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid3
{
    uint32_t U;
    struct _hw_rom_periphid3_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_rom_periphid3_t;

/*!
 * @name Constants and macros for entire ROM_PERIPHID3 register
 */
/*@{*/
#define HW_ROM_PERIPHID3_ADDR(x) ((x) + 0xFECU)

#define HW_ROM_PERIPHID3(x)      (*(__I hw_rom_periphid3_t *) HW_ROM_PERIPHID3_ADDR(x))
#define HW_ROM_PERIPHID3_RD(x)   (HW_ROM_PERIPHID3(x).U)
/*@}*/

/*
 * Constants & macros for individual ROM_PERIPHID3 bitfields
 */

/*!
 * @name Register ROM_PERIPHID3, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_ROM_PERIPHID3_PERIPHID (0U)     /*!< Bit position for ROM_PERIPHID3_PERIPHID. */
#define BM_ROM_PERIPHID3_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for ROM_PERIPHID3_PERIPHID. */
#define BS_ROM_PERIPHID3_PERIPHID (32U)    /*!< Bit field size in bits for ROM_PERIPHID3_PERIPHID. */

/*! @brief Read current value of the ROM_PERIPHID3_PERIPHID field. */
#define BR_ROM_PERIPHID3_PERIPHID(x) (HW_ROM_PERIPHID3(x).U)
/*@}*/

/*******************************************************************************
 * HW_ROM_COMPIDn - Component ID Register
 ******************************************************************************/

/*!
 * @brief HW_ROM_COMPIDn - Component ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the component IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_compidn
{
    uint32_t U;
    struct _hw_rom_compidn_bitfields
    {
        uint32_t COMPID : 32;          /*!< [31:0] Component ID */
    } B;
} hw_rom_compidn_t;

/*!
 * @name Constants and macros for entire ROM_COMPIDn register
 */
/*@{*/
#define HW_ROM_COMPIDn_COUNT (4U)

#define HW_ROM_COMPIDn_ADDR(x, n) ((x) + 0xFF0U + (0x4U * (n)))

#define HW_ROM_COMPIDn(x, n)     (*(__I hw_rom_compidn_t *) HW_ROM_COMPIDn_ADDR(x, n))
#define HW_ROM_COMPIDn_RD(x, n)  (HW_ROM_COMPIDn(x, n).U)
/*@}*/

/*
 * Constants & macros for individual ROM_COMPIDn bitfields
 */

/*!
 * @name Register ROM_COMPIDn, field COMPID[31:0] (RO)
 *
 * Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to
 * 0x0000_0005; ID3 to 0x0000_00B1.
 */
/*@{*/
#define BP_ROM_COMPIDn_COMPID (0U)         /*!< Bit position for ROM_COMPIDn_COMPID. */
#define BM_ROM_COMPIDn_COMPID (0xFFFFFFFFU) /*!< Bit mask for ROM_COMPIDn_COMPID. */
#define BS_ROM_COMPIDn_COMPID (32U)        /*!< Bit field size in bits for ROM_COMPIDn_COMPID. */

/*! @brief Read current value of the ROM_COMPIDn_COMPID field. */
#define BR_ROM_COMPIDn_COMPID(x, n) (HW_ROM_COMPIDn(x, n).U)
/*@}*/

/*******************************************************************************
 * hw_rom_t - module struct
 ******************************************************************************/
/*!
 * @brief All ROM module registers.
 */
#pragma pack(1)
typedef struct _hw_rom
{
    __I hw_rom_entryn_t ENTRYn[3];         /*!< [0x0] Entry */
    __I hw_rom_tablemark_t TABLEMARK;      /*!< [0xC] End of Table Marker Register */
    uint8_t _reserved0[4028];
    __I hw_rom_sysaccess_t SYSACCESS;      /*!< [0xFCC] System Access Register */
    __I hw_rom_periphid4_t PERIPHID4;      /*!< [0xFD0] Peripheral ID Register */
    __I hw_rom_periphid5_t PERIPHID5;      /*!< [0xFD4] Peripheral ID Register */
    __I hw_rom_periphid6_t PERIPHID6;      /*!< [0xFD8] Peripheral ID Register */
    __I hw_rom_periphid7_t PERIPHID7;      /*!< [0xFDC] Peripheral ID Register */
    __I hw_rom_periphid0_t PERIPHID0;      /*!< [0xFE0] Peripheral ID Register */
    __I hw_rom_periphid1_t PERIPHID1;      /*!< [0xFE4] Peripheral ID Register */
    __I hw_rom_periphid2_t PERIPHID2;      /*!< [0xFE8] Peripheral ID Register */
    __I hw_rom_periphid3_t PERIPHID3;      /*!< [0xFEC] Peripheral ID Register */
    __I hw_rom_compidn_t COMPIDn[4];       /*!< [0xFF0] Component ID Register */
} hw_rom_t;
#pragma pack()

/*! @brief Macro to access all ROM registers. */
/*! @param x ROM module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 *     use the '&' operator, like <code>&HW_ROM(ROM_BASE)</code>. */
#define HW_ROM(x)      (*(hw_rom_t *)(x))

#endif /* __HW_ROM_REGISTERS_H__ */
/* v33/140401/2.1.0 */
/* EOF */
